This invention is in the field of integrated circuits, and is specifically directed to the process of forming a bipolar transistor structure that is compatible with the formation of CMOS structures on a single semiconductor substrate.
The integration of MOSFET structures and bipolar transistors on a single substrate has become very desirable. In addition, silicon on insulator (SOI) technology offers the highest performance for a given feature size due to the minimization of parasitic capacitance.
As is well known in the art, digital and linear functions are often performed by integrated circuits using either bipolar or metal-oxide-semiconductor (MOS) technology. Bipolar integrated circuits, of course, provide higher speed operation and greater drive currents than the MOS circuits, at the cost of higher power dissipation, especially when compared against complementary MOS (CMOS) circuits. Recent advances in manufacturing technology have allowed the use of both bipolar and CMOS transistors in the same integrated circuit (commonly referred to as BiCMOS devices). Further exploitation of the high current driving capabilities of the bipolar transistor is important to obtaining even higher levels of bipolar or merged bipolar CMOS integration.
To date, SOI processes have been CMOS oriented. For bipolar or BICMOS processes in SOI, typical problems have been the defect density caused by the buried oxide layer. Various approaches to SOI bipolar structures have been demonstrated but these approaches suffer from the limitation that they require trench isolation which, in addition to being an expensive process, trench isolation tends to be a yield limiting process in manufacturing.